1. Field of the Invention
The present invention relates to a parallel-serial data converter and particularly relates to a parallel-serial data converter which converts parallel data in sign magnitude notation into serial data in two's complement notation.
2. Description of the Related Art
As shown in FIG. 9, a parallel-serial data converter to convert parallel data in sign magnitude notation into serial data in two's complement notation generally comprises EXOR (exclusive-OR) circuits 90.sub.1, . . . , 90.sub.n-2 and 90.sub.n-1, adders 91.sub.1, . . . , 91.sub.n-2 and 91.sub.n-2, selectors 92.sub.1, . . . , 91.sub.n-2 and 91.sub.n-1, latch circuits 93.sub.1, . . . , 93.sub.n-2 and 93.sub.n-1 and another latch circuit 93.sub.n, an OR circuit 94, AND circuits 95 and 96 and a still another latch circuit 97. From n (positive integer) bits of parallel data in sign magnitude notation I.sub.1, . . . , I.sub.n-2, I.sub.n-1 and I.sub.n, the sign bit I.sub.n and each of the remaining bits I.sub.1 to I.sub.n-1 are sent to the EXOR circuits 90.sub.1, . . . , 90.sub.n-2 and 90.sub.n-1 respectively. The outputs from the EXOR circuits 90.sub.1, . . . , 90.sub.n-2 and 90.sub.n-1 are sent to the adders 91.sub.1, . . . , 91.sub.n-2 and 91.sub.n-2 where the carry output from less significant bit is treated as the carry input. The addition results from the adders and the outputs from the latch circuits 93.sub.1, . . . , 93.sub.n-2, 93.sub.n-1 and 93 n are given as inputs A and B to the selectors 92.sub.1, . . . , 92.sub.n-2 and 92.sub.n-1, each of which selects either of A or B according to the STORE signal. The outputs from the selectors 92.sub.1, . . . , 92.sub.n-2 and 92.sub.n-1 are input to the latch circuits 93.sub.1, 93.sub.n-2 and 93.sub.n-1. The latch circuit 93.sub.n receives the sign bit I.sub.n as the data input. The OR circuit 94 takes the logical OR the STORE and LOAD signals. The AND circuit 95 takes the logical AND the output from the OR circuit 94 and the CLOCK (1) signal, and the AND circuit 96 takes the logical AND the output from the OR circuit 94 and the CLOCK (2) signal. The latch circuit 97 outputs serial data.
Each of the latch circuits 93.sub.n to 93.sub.1 and the latch circuit 97 comprises a two-phase flip-flop of D type and receives the output from the AND circuit 95 as the master clock and the output from the AND circuit 96 as the slave clock.
FIG. 10 is a timing chart of input/output signals for such a conventional embodiment. Referring to FIGS. 9 and 10, the operation in a conventional embodiment will be described below.
Firstly, when the parallel data I.sub.1 to I.sub.n in sign magnitude notation are positive, the sign bit I.sub.n is at "L" level. The parallel data I.sub.1, . . . , I.sub.n-2 and I.sub.n-1 in sign magnitude notation are output as they are from the EXOR circuits 90.sub.1, . . . , 90.sub.n-2 and 90.sub.n-1 serving as discrepancy detectors. They are sent to the corresponding adders 91.sub.1, . . . 91.sub.n-2 and 91.sub.n-1 and output as they are again. If the STORE signal is at H level, the selectors 92.sub.1, . . . , 92.sub.n-2 and 92.sub.n-1 select input A for output, which causes the outputs from the adders 91.sub.1, . . . , 91.sub.n-2 and 91.sub.n-1 to be sent to the latch circuits 93.sub.1, . . . , 93.sub.n-1. The latch circuit 93 n directly fetches the sign bit I.sub.n. If the LOAD signal is at H level, the selectors 92.sub.1, . . . , 92.sub.n-2 and 92.sub.n-1 select input B for output and each time the CLOCK signal (2) rises, latch data from the latch circuits 93.sub.1 to 93.sub.n are subsequently output from the latch circuit 97 as serial data in two's complement notation.
Next, when the parallel data I.sub.1 to I.sub.n in sign magnitude notation are negative, the sign bit I.sub.n is at "H" level. The parallel data I.sub.1, . . . , I.sub.n-2 and I.sub.n-1 in sign magnitude notation are, at the EXOR circuits 90.sub.1, . . . , 90.sub.n-2, 90.sub.n-1 serving as discrepancy detectors, output with the level reversed and sent to the corresponding adders 91.sub.1, . . . , 91.sub.n-2 and 91.sub.n-1 for addition and output. If the STORE signal is at H level, the selectors 92.sub.1, 92.sub.n-2 and 92.sub.n-1 select input A for output and the outputs from the adders 91.sub.1, . . . and 91.sub.n-2, 91.sub.n-1 are sent to the latch circuits 93.sub.1, . . . and 93.sub.n-1. The latch circuit 93.sub.n directly fetches the sign bit I.sub.n. If the LOAD signal is at H level, the selectors 92.sub.1, . . . , 92.sub.n-2 and 92.sub.n-1 select input B for output. As a result, the data from the latch circuits 93.sub.1 to 93.sub.n are output from the latch circuit 97 as serial data in two's complement notation.
Thus, parallel data in sign magnitude notation are converted into and output as serial data in two's complement notation when two is at the LSB first. In such a conventional parallel-serial data converter, the operation to convert parallel data in sign magnitude notation into serial data in two's complement notation applies to the parallel data. This means that the converter must have as many EXOR circuits and adders as the number of bits contained in the data to be converted. This may result in a huge circuit scale.